This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to static random access memory (SRAM) cells and devices.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM and in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
An example of a conventional SRAM cell is shown in FIG. 1a. In this example, SRAM cell 12 is a conventional six-transistor (6-T) static memory cell 12, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 12 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 12 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 13a and n-channel driver transistor 14a, and the other inverter of series-connected p-channel load transistor 13b and n-channel transistor 14b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 13a, 14a constitutes storage node SNT, and the common drain node of transistors 13b, 14b constitutes storage node SNB, in this example. N-channel pass transistor 15a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass transistor 15b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass transistors 15a, 15b are driven by word line WLj for this jth row in which cell 12 resides.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage at the beginning of both read and write cycles, after which bit lines BLTk, BLBk then float at that precharged voltage. To access cell 12 for a read operation, word line WLj is then energized, turning on pass transistors 15a, 15b, and connecting storage nodes SNT, SNB to the then-floating precharged bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of then-floating precharged bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 12 to latch in the desired state.
As mentioned above, device variability can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, in an attempt to write a low logic level to storage node SNT, if bit line BLTk is unable to sufficiently discharge storage node SNT to trip the inverter of transistors 13b and 14b, cell 12 may not latch to the desired data state. Cell stability failures are the converse of write failures—a write failure occurs if a cell is too stubborn in changing its state, while a cell stability failure occurs if a cell changes its state too easily.
One conventional approach toward satisfying both cell stability and write margin constraints is the construction of high performance SRAM memories using eight transistor (“8-T”) memory cells. An example of this 8-T construction is illustrated in FIG. 1b in connection with SRAM cell 12′j,k (in row j and column k, as before), which includes a 6-T latch in combination with a two-transistor read buffer. Cell 12′j,k includes the 6-T latch of transistors 13p, 13n, 14p, 14n, 15a, 15b, as described above relative to FIG. 1b. However, in cell 12′j,k, write word line WWLj is connected to the gates of pass transistors 15a, 15b, and is asserted only in write cycles to row j, by way of which storage nodes SNT, SNB are connected to complementary write bit lines WBLTk, WBLBk for column k. In a write to cell 12′j,k, write circuitry (not shown) pulls one of write bit lines WBLTk, WBLBk to ground, depending on the data state being written into cell 12′j,k.
The read buffer of 8-T cell 12′j,k includes n-channel transistors 16n, 18n, which have their source-drain paths connected in series between read bit line RBLk and ground. Read buffer pass transistor 18n has its drain connected to read bit line RBLk, and its gate receiving read word line RWLj for row j. Read buffer driver transistor 16n has its drain connected to the source of transistor 18n and its source at ground; the gate of transistor 16n is connected to storage node SNB. In a read of cell 12′j,k, read word line RWLj is asserted active high, which turns on buffer pass transistor 18n. If the data state of storage node SNB is a “1”; then read bit line RBLk is pulled to ground by buffer driver transistor 16n through buffer pass transistor 18n. Conversely, if the data state of storage node SNB is a “0”, transistor 16n remains off and read bit line RBLk is not pulled down. A sense amplifier (not shown) is capable of detecting whether read bit line RBLk is pulled to ground by the selected cell in column k, and in turn communicates that data state to I/O circuitry as appropriate.
In this 8-T construction, the pass transistors involved in the write cycle can have strong drive to provide good write margin, without affecting cell stability during read operations (because those pass transistors remain off). However, both the conventional 6-T cell of FIG. 1a and the conventional 8-T cell of FIG. 1b are vulnerable to unintentional change of state during the writing of data to other cells. More specifically, it has been observed that SRAM cells in unselected columns of selected rows (i.e., “half-selected” cells) are especially vulnerable to the “disturb” condition present on their bit lines during writes to cells in the same row. This disturb situation will now be described in connection with FIG. 1c. 
FIG. 1c illustrates an example of a conventional interleaved array 19 of conventional 8-T SRAM cells 12′, as described above relative to FIG. 1b. In the arrangement of FIG. 1c, a pair of write bit lines and a read bit line (not shown in FIG. 1c) are shared by each column of SRAM cells 12′, and extend between precharge/equalization circuitry 22 and column select multiplexers 23, with SRAM cells 12′ in that column connected to those bit lines in the manner described above relative to FIG. 1b. SRAM cells 12′ are also arranged in rows, with each row of cells 12′ sharing one of read word lines RWL0 through RWL3, and one of write word lines WWL0 through WWL3. In a read cycle, one of read word lines RWL0 through RWL3 is driven active by a row decoder and word line driver (not shown), in response to a row address value. Similarly, in a write cycle, the one of write word lines WWL0 through WWL3 corresponding to the row address is driven active by the row decoder and word line driver.
The architecture shown in FIG. 1c is referred to as interleaved, in that the columns are grouped such that the addressing of a data word selects one column in each group of columns, along the selected row. In this example, one group of four columns is shown, such that a given column address value selects one column from each group. Of course, array 19 will typically include more than the four columns and three rows of SRAM cells 12′ shown in FIG. 1c. This interleaving is accomplished, in this conventional architecture, by column select multiplexer 23 associated with the four adjacent columns of cells 12′ of FIG. 1c. Column select multiplexers 23 selects one column from its group of four in response to the state of the least significant two column address bits CA[1:0], as applied by column decode circuitry (not shown). The column selected by column select multiplexer 23 is placed in communication with read/write circuit 25. In this architecture, read/write circuit 25 is connected to a corresponding input/output line D/Q, as shown. Typical interleaved architectures will include multiple column select multiplexers 23 and read/write circuits 25, to accommodate the number of columns present in array 19 (arranged in groups of four columns, in this example).
FIG. 1c illustrates an example of a write cycle being applied to SRAM cell 12′[SEL] in array 19. In this example, selected SRAM cell 12′[SEL] is in the row associated with write word line WWL1, in the fourth column in the group of columns associated with read/write circuit 25 (i.e., column address bits CA[1:0] both carry a “1” logic level). Other cells 12′ [HS] that are in this same row associated with write word line WWL1, but that are in the unselected columns, are referred to as “half-selected”. During a write to selected SRAM cell 12′[SEL], pass transistors 15a, 15b (FIG. 1b) for each of these half-selected cells 12′[HS] will be turned on by write word line WWL1, connecting their respective storage nodes SNT, SNB to the unselected write bit lines WBLT, WBLB. However, because these columns are not selected for the write cycle, neither of those write bit lines WBLT, WBLB for the half-selected columns will be driven low by read/write circuit 25, but will remain floating at its precharged voltage.
It has been observed that this half-selection can upset the stored state of half-selected cells 12′[HS]. The initial high voltage at the one of the floating bit lines coupled to the “0” state storage node injects DC noise current at that storage node, which tends to pull up the voltage at that storage node from its initial “0” level, for example to about 20 to 30% of power supply voltage Vdda. This effect can upset the stored data state, particularly for half-selected cells in which the transistors are imbalanced due to process variations. In addition, noise of sufficient magnitude coupling to the bit lines of the half-selected columns, during a write to the selected columns in the same row, can cause a false write of data to those half-selected columns. In effect, such write cycle noise can be of sufficient magnitude as to trip the inverters of one or more of the half-selected cells 12′ [HS]. The possibility of such stability failure is exacerbated by device mismatch and variability, as discussed above.
In conventional SRAM cells such as 6-T SRAM cell 12 of FIG. 1a and 8T SRAM cell 12′ of FIG. 1b, the designer is therefore faced with a tradeoff between cell stability on one hand, and write margin on the other. In a general sense, cell stability is favored by pass transistors 15a, 15b having relatively weak drive as compared with load transistors 13 and driver transistors 14, because this results in weak coupling between the bit lines and storage nodes and relatively strong drive of the latched state at storage nodes SNT, SNB. Conversely, write margin is favored by pass transistors 15a, 15b having relatively strong drive as compared with load transistors 13 and driver transistors 14, because this enables strong coupling between the bit lines and storage nodes, resulting in storage nodes SNT, SNB having weak resistance to changing state. Accordingly, the design of conventional 6-T SRAM cells 12 and 8-T SRAM cells 12′ involves a tradeoff between these two vulnerabilities.
Unfortunately, the design window in which both adequate cell stability and adequate write margin can be attained is becoming smaller with continued scaling-down of device feature sizes, for the reasons mentioned above. In addition, it has been observed that the relative drive capability of p-channel MOS transistors relative to re-channel MOS transistors is increasing as device feature sizes continue to shrink, which skews the design window toward cell stability over write margin.
By way of further background, the 8-T concept described in connection with FIG. 1b is further extended, in some conventional SRAM memories, to provide complementary read bit lines, supporting differential sensing of the stored data state in a read cycle. An example of this extended structure is illustrated by way of cell 12″j,k shown in FIG. 1d. Cell 12″j,k includes the eight transistors of cell 12′j,k shown in FIG. 1b, but also includes transistors 16n′, 18n′ that forward the data state at storage node SNT to complementary read bit line RD_BLBk, in similar fashion as transistors 16n, 18n forward the state at storage node SNB to read bit line RD_BLTk. In a read cycle, enabled by read word line RD WLj driven active high, which turns on transistors 18n, 18n′, a differential signal is generated on read bit lines RD_BLBk, RD_BLTk according to the states at storage nodes SNT, SNB. SRAM cells constructed as shown in FIG. 1c are referred to in the art as “10-T” cells. However, because pass transistors 15a, 15b are turned on for unselected columns in selected row j, cell 12″j,k also suffers from the cell stability, or disturb vulnerability, described above.
By way of further background, my copending and commonly assigned U.S. patent application Ser. No. 12/827,706, filed Jun. 24, 2010, entitled “Bit-by-Bit Write Assist for Solid-State Memory”, describes a solid-state memory in which write assist circuitry is implemented within each memory cell. As described in this application, each memory cell includes a pair of power switch transistors that selectably apply bias (either power supply voltage Vdd or ground) to the inverters of the memory cell. One of the power switch transistors is gated by a word line indicating selection of the row containing the cell, and the other is gated by a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to the cell, both power switch transistors are turned off, removing bias from the inverter. With bias removed from the inverters, the writing of an opposite cell state is facilitated.
By way of further background, my copending and commonly assigned U.S. patent application Ser. No. 12/834,914, filed Jul. 13, 2010, entitled “Memory Cell with Equalization Write Assist Solid-State Memory”, describes a solid-state memory in which equalization transistors are included within each memory cell. In each selected memory cell in a write cycle, those equalization transistors are turned on to short the storage nodes to one another. The bit line driven by the write circuitry can then more readily define the state of the cross-coupled inverters, by eliminating the tendency of those inverters to maintain the previously stored latch state.
By way of further background, my copending and commonly assigned U.S. patent application Ser. No. 13/104,735, filed May 10, 2011, entitled “Solid-State Memory Cell with Improved Read Stability”, describes a solid-state memory in which an isolation gate, for example realized by parallel-connected complementary MOS transistors, is included within each memory cell. The isolation gate within an SRAM cell is connected between the input to one of the cross-coupled inverters and the opposite storage node. As described in that copending application, the isolation gate is turned off in read cycles, and for unselected columns in write cycles. The isolation gate, when turned off, eliminates modulation at one of the storage nodes from affecting the state of the opposite inverter, breaking the feedback loop for bit line noise and inhibiting stability failures.
By way of further background, Takeda et al., “A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications”, J. Solid-State Circuits, Vol. 41, No. 1 (IEEE, January 2006), pp. 113-21, describes a seven-transistor (7-T) SRAM cell in which an additional transistor is included in series with one of the inverters, and is gated by the word line. The inverter that includes the extra series transistor has its common drain node coupled to its bit line only in write cycles (i.e., by a “write word line”); the opposing inverter drives its bit line in read cycles. This single-ended read limits the number of cells that can connect to the same bit line, because of the reduced read signal strength. The chip area efficiency is thus impacted by that constraint, and also because of the three separate word lines that must now be routed to each cell. In addition, the asymmetric layout of the 7-T cell precludes implementation in an interleaved array architecture, increasing the likelihood of multiple-bit soft errors, and further reducing chip area efficiency.
By way of further background, FIG. 1e illustrates an example of conventional SRAM cell 12′″ of the “cross-point” type. The “cross-point” nomenclature refers to the requirement that both a word line and a column select line be energized to couple storage nodes SNT, SNB to bit lines BLT, BLB, respectively. Cell 12′″ is constructed similarly as 6-T SRAM cell described above relative to FIG. 1a, except that pass transistors 15a, 15b are arranged in series with a corresponding pass transistor 17a, 17b, respectively. More specifically, the source-drain paths of pass transistors 15a, 17a are connected in series between storage node SNT and bit line BLT, and the source-drain paths of pass transistors 15b, 17b are connected in series between storage node SNB and bit line BLB. The gates of pass transistors 15a, 15b are driven by word line WL, as before. The gates of pass transistors 17a, 17b are driven by column select line CS, as may be driven by a column select or column decoder circuit in the memory function.